PiSMA: an upgradable fault tolerant approach to parallel processing

Parallel processors reduce the communication overhead problem with the employment of some form of global communication network. This network however, imposes restrictions on the scaleability and technological evolution of the parallel processor. In this paper a novel architecture called PiSMA is proposed, which consists of a basic substrate, without a network, providing neighborhood connectivity for local communication. The same architecture can be upgraded, by the addition of a global network. The simulated performance of such an upgradeable parallel computer is measured with a wide range of parallel applications and fault tolerant issues are discussed. It is found that the substrate connectivity can provide an effective fault tolerant parallel computer for a large class of applications, while the incorporation of a global network broadens the spectrum of applications that can be executed efficiently by the PiSMA architecture.